27 #if defined(ASCON_MASKED_X2_BACKEND_C32)
37 #define and_not_xor(x, y, z, w) \
39 x##_a##w ^= ((~y##_a##w) & ascon_mask32_unrotate_share1_0(z##_b##w)); \
40 x##_a##w ^= ((~y##_a##w) & z##_a##w); \
41 x##_b##w ^= (y##_b##w & z##_b##w); \
42 x##_b##w ^= (y##_b##w & ascon_mask32_rotate_share1_0(z##_a##w)); \
52 t0 = x0_##w##e ^ rightRotate4(x0_##w##o); \
53 t1 = x0_##w##o ^ rightRotate5(x0_##w##e); \
54 t2 = x1_##w##e ^ rightRotate11(x1_##w##e); \
55 t3 = x1_##w##o ^ rightRotate11(x1_##w##o); \
56 t4 = x2_##w##e ^ rightRotate2(x2_##w##o); \
57 t5 = x2_##w##o ^ rightRotate3(x2_##w##e); \
58 t6 = x3_##w##e ^ rightRotate3(x3_##w##o); \
59 t7 = x3_##w##o ^ rightRotate4(x3_##w##e); \
60 t8 = x4_##w##e ^ rightRotate17(x4_##w##e); \
61 t9 = x4_##w##o ^ rightRotate17(x4_##w##o); \
62 x0_##w##e ^= rightRotate9(t1); \
63 x0_##w##o ^= rightRotate10(t0); \
64 x1_##w##e ^= rightRotate19(t3); \
65 x1_##w##o ^= rightRotate20(t2); \
67 x2_##w##o ^= rightRotate1(t4); \
68 x3_##w##e ^= rightRotate5(t6); \
69 x3_##w##o ^= rightRotate5(t7); \
70 x4_##w##e ^= rightRotate3(t9); \
71 x4_##w##o ^= rightRotate4(t8); \
76 #define ROUND_CONSTANT_PAIR(rc1, rc2) \
77 (~((uint32_t)(rc1))), (~((uint32_t)(rc2)))
82 static const uint32_t RC[12 * 2] = {
96 const uint32_t *rc = RC + first_round * 2;
97 uint32_t x0_ae, x1_ae, x2_ae, x3_ae, x4_ae;
98 uint32_t x0_ao, x1_ao, x2_ao, x3_ao, x4_ao;
99 uint32_t x0_be, x1_be, x2_be, x3_be, x4_be;
100 uint32_t x0_bo, x1_bo, x2_bo, x3_bo, x4_bo;
101 uint32_t t0_ao, t0_bo, t1_ao, t1_bo;
102 uint32_t t0_ae, t0_be, t1_ae, t1_be;
103 uint32_t t6, t7, t8, t9;
106 t0_ae = ((uint32_t *)preserve)[0];
107 t0_ao = ((uint32_t *)preserve)[1];
138 while (first_round++ < 12) {
232 ((uint32_t *)preserve)[0] = t0_ae;
233 ((uint32_t *)preserve)[1] = t0_ao;
244 state->M[2].
W[0] = ~x2_ae;
245 state->M[2].
W[1] = ~x2_ao;
#define ROUND_CONSTANT_PAIR(rc1, rc2)
Utility functions for operating on masked ASCON states with between 2 and 4 shares.
void ascon_x2_permute(ascon_masked_state_t *state, uint8_t first_round, uint64_t *preserve)
Permutes the ASCON-x2 state with a specified number of rounds.
#define ascon_mask32_rotate_share1_0(x)
Rotates 32-bit masked share 1 with respect to share 0.
#define and_not_xor(x, y, z)
Computes x ^= (~y & z) with a 2-share masked representation.
ascon_state_t state
[snippet_key]
State of the ASCON permutation which has been masked with up to 4 shares.