23 #ifndef ASCON_MASKED_BACKEND_H
24 #define ASCON_MASKED_BACKEND_H
32 #if defined(ASCON_BACKEND_AVR5)
35 #define ASCON_MASKED_X2_BACKEND_AVR5 1
36 #define ASCON_MASKED_X3_BACKEND_AVR5 1
37 #define ASCON_MASKED_WORD_BACKEND_DIRECT_XOR 1
39 #elif defined(ASCON_BACKEND_X86_64)
42 #define ASCON_MASKED_X2_BACKEND_X86_64 1
43 #define ASCON_MASKED_X3_BACKEND_X86_64 1
44 #define ASCON_MASKED_X4_BACKEND_X86_64 1
45 #define ASCON_MASKED_WORD_BACKEND_X86_64 1
46 #define ASCON_MASKED_BACKEND_SLICED64 1
48 #elif defined(ASCON_BACKEND_SLICED32)
53 #define ASCON_MASKED_X2_BACKEND_C32 1
54 #define ASCON_MASKED_X3_BACKEND_C32 1
55 #define ASCON_MASKED_X4_BACKEND_C32 1
56 #define ASCON_MASKED_WORD_BACKEND_C32 1
57 #define ASCON_MASKED_BACKEND_SLICED32 1
62 #define ASCON_MASKED_X2_BACKEND_C64 1
63 #define ASCON_MASKED_X3_BACKEND_C64 1
64 #define ASCON_MASKED_X4_BACKEND_C64 1
65 #define ASCON_MASKED_WORD_BACKEND_C64 1
66 #define ASCON_MASKED_BACKEND_SLICED64 1
Configures the number of shares to use for masked AEAD modes.